general description the max4885e integrates high-bandwidth analogswitches and level-translating buffers to implement a complete 1:2 multiplexer for vga signals. the device provides switching for rgb, display data channel (ddc). horizontal and vertical synchronization (hsync/vsync) inputs feature level-shifting buffers to support low-volt- age cmos or standard ttl-compatible graphics con- trollers, meeting the vesa requirement of ?ma. ddc, consisting of sda_ and scl_, is a bidirectional active- level translating switch that reduces capacitive load. the max4885e features high esd protection to ?5kv human body model (hbm) on all twelve externally rout- ed terminals. see the pin description section. all other pins are protected to ?0kv human body model (hbm).the max4885e is specified over the extended -40? to +85? temperature range, and is available in the 24-pin, 4mm x 4mm tqfn package. applications notebook computers/docking stationsdigital projectors computer monitors servers/storage kvm switches features ? 15kv hbm esd protection on externally routedterminals ? 1ghz bandwidth ? low 5 (typ) on-resistance (r, g, b signals) ? low 6pf (typ) on-capacitance (r, g, b signals) ? low r, g, b skew -50ps (typ) ? near zero power consumption (< 2a) ? ultra-small, 24-pin (4mm x 4mm) tqfn package max4885e ultra-low capacitance 1:2 vga switch with 15kv esd ________________________________________________________________ maxim integrated products 1 19-4269; rev 0; 10/08 evaluation kit available tqfn-ep max4885e 1920 21 22 12 3456 18 17 16 15 14 13 2324 1211 10 98 7 scl2 sda2 scl1 sda1 sel sda0 scl0 r0 g0 b0 h0 r1r2 g2 b1b2 en v1gnd h1v l v0 v cc g1 top view + *exposed pad. connected to ground or leave unconnected. *ep pin configuration ordering information graphics controller docking station vga port v l v cc gnd +3.3v en r0, b0, g0 h0, v0 sda0, scl0 r2, g2, b2 sda2, scl2 r1, g1, b1 sda1, scl1 h1, v1 3 2 2 3 2 2 2 3 2 sel docking station +5.0v +3.3v 0.1 f 0.1 f max4885e typical operating circuit part temp range pin-package max4885eetg+ -40? to +85? 24 tqfn-ep* * ep = exposed pad. + denotes lead-free package/rohs-compliant package. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim's website at www.maxim-ic.com. downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.)v cc , v l .....................................................................-0.3v to +6v r_, g_, b_, sda1, scl1, sda2, scl2, h1, v1, (note 1) ........................................-0.3v to v cc + 0.3v h0, v0, sda0, scl0, en, sel.........................-0.3v to v l + 0.3v continuous current through rgb switches .....................?0ma continuous current through ddc switches .....................?0ma peak current through rgb switches (pulsed at 1ms, 10% duty cycle)...................................?0ma peak current through ddc switches (pulsed at 1ms, 10% duty cycle)............................................................?0ma continuous power dissipation (t a = +70?) 24-pin tqfn (derate 27.8mw/? above +70?) ........2222mw junction to ambient thermal resistance ( ja ) (note 2) 24-pin tqfn..................................................................36?/w junction to ambient thermal resistance ( jc ) (note 2) 24-pin tqfn....................................................................3?/w operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? electrical characteristics(v cc = +5.0v ?0%, v l = +2v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v and t a = +25?.) (note 3) parameter symbol conditions min typ max units en = v l v cc quiescent supply current i cc v cc = +5.0v en = gnd 1 a en = v l v l quiescent supply current i vl v l = +3.3v en = gnd 1 a rgb analog switches on-resistance r on v cc = +5.0v, i in = -10ma, v in = +0.7v (note 4) 6 on-resistance matching ? r on 0 v in 0.7v, i in = -10ma 0.5 on-resistance flatness r flat ( on ) 0 v in 0.7v, i in = -10ma 0.5 off-leakage current i l(off) v cc = +5.5v, v in = +0.3v or +5.5v, v en = 0 or v l -1 +1 ? on-leakage current i l(on) v cc = +5.5v, v in = +0.3v or +5.5v, v en = v l -1 +1 ? hv buffer input voltage low v ilhv 0.33 x v l v input voltage high v ihhv 0.66 x v l v input logic hysteresis v hyst 75 mv input leakage current i inhv v cc = +5.5v, v l = +5.5v, v in = 0 or v l -1 +1 ? high-output drive current i ohhv v ohhv 3.0v 8.0 ma low-output drive current i olhv v olhv 0.6v 8.0 ma note 1: signals exceeding v cc or gnd are clamped by internal diodes. limit forward-diode current to maximum current rating. note 2: package thermal resistances were obtained using the method described in jedec specifications. for detailed informationon package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units sda_, scl_ supply voltage v l 2.0 5.5 v on-resistance r on v in = +0.4v, i in = ?ma, v l = +2.0v 10 on-capacitance c on f = 100khz 15 pf high-impedance input leakagecurrent i inhiz en = gnd, v cc = +5.5v, v l = +3.6v, scl0, sda0, scl1, scl2, sda1, sda2= gnd or v vl (note 5) -1 +1 ? off-input leakage current i inoff en = v l , v l = +3.6v, v in = v l - 0.2v -1 +1 ? control logic (sel, en) input voltage low v illog 0.33 x v l v input voltage high v ihlog 0.66 x v l v input logic hysteresis v hyst 75 mv input leakage current i inlek v cc = +5.5v, v l = +3.6v, v in = 0 or v l -1 +1 ? esd protection human body model; r1, g1, b1, r2, g2,b2, sda1, scl1, sda2, scl2, h1, v1 ?5 esd protection human body model; all other pins ?0 kv electrical characteristics (continued)(v cc = +5.0v ?0%, v l = +2v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v and t a = +25?.) (note 3) parameter symbol conditions min typ max units bandwidth f max r s = r l = 50 1g h z insertion loss i los f = 1mhz, r s = r l = 50 , figure 1 0.6 db crosstalk v ct f = 50mhz, r s = r l = 50 , figure 1 -40 db off-capacitance c off f = 250mhz 4.5 pf on-capacitance c on f = 250mhz 6.4 pf ac electrical characteristics(v cc = +5.0v ?0%, v l = +2v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v and t a = +25?.) (note 3) downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units rgb analog switches output skew between ports t skew skew between any two ports: r_, g_, b_,figure 2 50 ps hv buffer propagation delay t pd r l = 1k , c l = 10pf, figure 2 15 ns timing characteristics(v cc = +5.0v ?0%, v l = +2v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v and t a = +25?.) (note 3) note 3: all devices are 100% production tested at t a = +25?. specifications over the full temperature range are guaranteed by design. note 4: on-resistance guarantees the low-static logic level. note 5: sda_, scl_ off-input leakage current guarantees the high-static logic level. r on vs. v r0 * (rgb switches) max4885e toc01 v r0 (v) r on ( ) 0.8 0.6 0.4 0.2 1 2 3 4 5 6 7 8 9 10 0 01 0.7 0.5 0.3 0.1 0.9 t a = +85 c t a = +25 c t a = -40 c *r0, g0, b0 are interchangeable r on vs. v sda0 * (ddc switches) max4885e toc02 v sda0 (v) r on ( ) 1.0 1.5 3.0 4.0 15 30 45 60 0 04 . 5 2.5 2.0 3.5 0.5 t a = +85 c t a = +25 c t a = -40 c t a = +85 c v l = +3.3v v l = +5.0v t a = +25 c t a = -40 c sda0, scl0 areinterchangeable hv buffer output voltage high vs. temperature max4885e toc03 temperature ( c) output voltage high (v) 35 54 6 7 83 -40 85 -15 60 10 i out = 8ma typical operating characteristics (v cc = +5.0v, v l = +3.3v and t a = +25?, unless otherwise noted.) downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd _______________________________________________________________________________________ 5 hv buffer output voltage low vs. temperature max4885e toc04 temperature ( c) output voltage low (v) 35 0.40.2 0.6 0.8 1.00.0 -40 85 -15 60 10 i out = 8ma supply current vs. temperature max4885e toc05 temperature ( c) supply current ( a) 35 0.20.1 0.3 0.4 0.50.0 -40 85 -15 60 10 i cc i vl typical operating characteristics (continued) (v cc = +5.0v, v l = +3.3v and t a = +25?, unless otherwise noted.) on-response vs. frequency max4885e toc06 frequency (mhz) on-response (db) 10 -6-8 -4 -2 0 -10 -5-7 -3 -1-9 1 1000 100 crosstalk vs. frequency max4885e toc07 frequency (mhz) crosstalk (db) 10 -60-80 -40 -20 0 -100 -50-70 -30 -10-90 1 1000 100 downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd 6 _______________________________________________________________________________________ timing circuits/timing diagrams input output v oh t phl t plh t skew = |t plh - t phl | t pd = max (t plh , t phl ) 1v 50% 0 50% 0.9v 50% 50% 0 r l = 1k c l = 10pf figure 2. propagation delay and skew waveforms measurements are standardized against shorts at ic terminals. insertion-loss is measured between r0 and r1 or r2 on each switch. crosstalk is measured from one channel to the other channel. signal direction through switch is reversed; worst values are recorded. +5v v out v cc sel v in max4885e crosstalk = 20log v out v in network analyzer 50 50 50 50 meas ref 10nf 0 or v cc 50 gnd r0, g0, b0 r2, g2, b2 r1, g1, b1 insertion-loss = 20log v out v in figure 1. insertion-loss and crosstalk downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd _______________________________________________________________________________________ 7 pin description pin name function 1 sda0 sda i/o 2 scl0 scl i/o 3 r0 rgb analog i/o 4 g0 rgb analog i/o 5 b0 rgb analog i/o 6 h0 horizontal sync input 7 v0 vertical sync input 8v cc supply voltage. v cc = +5.0v ?0%. bypass v cc to gnd with a 0.1? or larger ceramic capacitor. 9v l supply voltage. +2v v l +5.5v. bypass v l to gnd with a 0.1? or larger ceramic capacitor. 10 gnd ground 11 h1 horizontal sync output* 12 v1 vertical sync output* 13 b2 rgb analog i/o* 14 b1 rgb analog i/o* 15 g2 rgb analog i/o* 16 g1 rgb analog i/o* 17 r2 rgb analog i/o* 18 r1 rgb analog i/o* 19 scl2 scl i/o* 20 scl1 scl i/o* 21 sda2 sda i/o* 22 sda1 sda i/o* 23 en enable input. drive en high for normal operation. drive en low to disable the device. 24 sel select input. logic input for switching rgb and ddc swiches. ep exposed pad. connect exposed pad to ground or leave unconnected. detailed description the max4885e integrates high-bandwidth analogswitches and level-translating buffers to implement a complete 1:2 multiplexer for vga signals. the device provides switching for rgb, hsync, vsync, sda_ and scl_ signals. the hsync and vsync inputs feature level-shifting buffers to support ttl output logic levels from low-volt- age graphics controllers. these buffered switches may be driven from as little as +2.0v up to +5.5v. rgb sig- nals are routed with the same high-performance analog switches, and sda_, scl_ signals are voltage clamped to a diode drop less than v l . voltage clamping pro- vides protection and compatibility with sda_ and scl_ signals and low-voltage asics. in keyboard/video/ mouse (kvm) applications, v l is normally set to +5v because low-voltage clamping is not required, as spec-ified by the vesa standard. drive en logic-low to shut down the max4885e. in shut- down mode, all switches are high impedance, providing high-signal rejection. the rgb, hsync, vsync, sda_, and scl_ outputs are esd protected to ?5kv by the human body model. rgb switches the max4885e provides three spdt high-bandwidthswitches to route standard vga r, g, and b signals (see table 1). the r, g, and b analog switches are identical, and any of the three switches can be used to route red, green, or blue video signals. * terminal as ?5kv esd protection?uman body model. downloaded from: http:///
horizontal/vertical sync level shifter hsync/vsync are buffered to provide level shiftingand drive capability to meet the vesa specification. display-data channel multiplexer the max4885e provides two voltage-clamped switchesto route ddc signals (see table 3). each switch clamps signals to a diode drop less than the voltage applied on v l . supply +3.3v on v l to provide voltage clamping for vesa i 2 c-compatible signals. if voltage clamping is not required, connect v l to v cc . the sda_ and scl_ switches are identical, and each switch can be used toroute either sda_ and scl_ signals. esd protection as with all maxim devices, esd-protection structuresare incorporated on all pins to protect against electro- static discharges encountered during handling and assembly. additionally, the max4885e is protected to ?5kv on rgb, hsync, vsync, sda_ and scl_ outputs by the human body model (hbm). see the pin description section. for optimum esd performance, bypass each v cc pin to ground with a 0.1? or larger ceramic capacitor. human body model (hbm) several esd testing standards exist for measuring therobustness of esd structures. the esd protection of the max4885e is characterized with the human body model. figure 3 shows the model used to simulate an esd event resulting from contact with the human body. the model consists of a 100pf storage capacitor that is charged to a high voltage, then discharged through a 1.5k resistor. figure 4 shows the current waveform when the storage capacitor is discharged into a lowimpedance. esd test conditions esd performance depends on a variety of conditions.please contact maxim for a reliability report document- ing test setup, methodology, and results. applications information the max4885e provides the level shifting necessary todrive two standard vga ports from a graphics con- troller as low as +2.2v. internal buffers drive the hsync and vsync signals to vga standard ttl lev- els. the ddc multiplexer provides level shifting by clamping signals to a diode drop less than v l (see the typical operating circuit ). connect v l to +3.3v for nor- mal operation, or to v cc to disable voltage clamping for ddc signals. power-supply decoupling bypass each v cc pin and v l to ground with a 0.1? or larger ceramic capacitor as close as possible to thedevice. pcb layout high-speed switches such as the max4885e requireproper pcb layout for optimum performance. ensure that impedance-controlled pcb traces for high-speed signals are matched in length and as short as possible. connect the exposed pad to a solid ground plane. chip information process: bicmos max4885e ultra-low capacitance 1:2 vga switch with 15kv esd 8 _______________________________________________________________________________________ en function 0 h_, v_ = 0 table 2. hv truth table x = don? care. en sel function 10 sda0 to sda1scl0 to scl1 11 sda0 to sda2scl0 to scl2 0 x sda_, scl_, high impedance table 3. ddc truth table x = don? care. en sel function 10 r0 to r1g0 to g1 b0 to b1 11 r0 to r2g0 to g2 b0 to b2 0 x r_, b_, and g_, high impedance table 1. rgb truth table x = don? care. downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd _______________________________________________________________________________________ 9 charge-current- limit resistor discharge resistance storagecapacitor c s 100pf r c 1m r d 1500 high- voltage dc source device under test figure 3. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing(not drawn to scale) i r 10% 0 0 amperes figure 4. hbm discharge current waveform r1g1 b1 r2 g2 r0 g0 b2h1 v1 b0 en sel h0 v0 bidirectional level shifter max4885e sda0 scl0 sda1 scl1 sda2 scl2 functional diagram downloaded from: http:///
max4885e ultra-low capacitance 1:2 vga switch with 15kv esd maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. package type package code document no. 24 tqfn-ep t2444-4 21-0139 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . downloaded from: http:///
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